One major concern associated with memory protection is the cost of address space switching. On ARM a context switch requires switching page tables. The complete cost of page table switch includes the cost of flushing page tables, purging TLBs and caches and then refilling them. Two mechanisms were introduced to enable operating system designers eliminate this cost in some cases.
- The first mechanism is protection domains. Every virtual memory page or sec-
tion belongs to one of sixteen protection domains. At any point in time, the
running process can be either a manager of a domain, which means that it can
access all pages belonging to this domain bypassing access permissions, a client
of the domain, which means that is can access pages belonging to the domain
according to their page table access permission bits, or can have no access to
the domain at all. In some situations, it is possible to do context switch by
simply changing domain access permissions, which means simply writing a new
value to the domain access register of coprocessor 15. - The second mechanism present in newer ARM cores is the fast context switch
extension (FCSE) that allows multiple processes to use identical address ranges,
while ensuring that the addresses they present to the rest of the memory system
differ. To that end, virtual addresses issued by a program within the first 32
megabytes of the address space are effectively augmented by the value of the
process identifier (PID) register. FCSE allows to avoid the overhead of purging
caches when performing a context switch; however it is still necessary to flush
TLBs.
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